1. Field of the Invention
This invention relates to active clamp circuits useful for reducing electrical overshoot and undershoot, for minimizing ringing and similar noise problems and for providing electrostatic discharge (ESD) protection, particularly in high speed metal oxide semiconductor (MOS) integrated circuit applications.
2. Description of Related Art
Clamping circuits are used to control electrical overshoot and undershoot at the signal input of a digital circuit to provide a reliable logic signal under adverse and noisy conditions. Ideally the input voltage to each element in a digital circuit will be in only one of two distinct logic states, either an upper digital voltage or a lower digital voltage, corresponding to the digital ones and zeros of the circuit. In such an ideal system, the input voltage will switch instantly between the up state and the down state, never going above the upper voltage nor below the lower voltage, and spending substantially no time at any intervening voltage between the two states.
In real circuits, however, the input voltage takes a finite amount of time to switch between the two states. Further, when switching between the two states, the input voltage will often overshoot the voltage corresponding to the new state, then oscillate (ring) around the new voltage before settling down.
Clamping circuits (which may also be referred to as termination networks) are designed to minimize the ringing which can seriously degrade circuit performance. A good clamping circuit should dampen ringing and reduce noise so that the signal at the input remains at or near one of the two desired voltage states and switches between those states quickly and cleanly.
Improved clamping performance comes about by supplying or draining current as quickly as possible to/from the network at the input to the circuit being clamped whenever the voltage at the input exceeds or falls below the desired voltage. In order to supply sufficient current, the clamping circuit should have low impedance and a low reflection coefficient in the vicinity of the upper and lower voltages corresponding to the two digital logic states.
On the other hand, in order to maximize switching speed between the two logic states, the impedance of the clamping circuit and the reflection coefficient should be very high during switching for the brief time when the input voltage is between the upper and lower digital voltages. Passive clamping circuits which are still widely used, are unable to effectively meet these opposing requirements for the highest performance applications.
Another requirement for digital circuits is some form of electrostatic discharge (ESD) protection. Generally, separate ESD protection circuits are provided at the input of the circuit to limit the voltage that can be imposed on the circuit at the input terminal even when the circuit is unpowered. It would be desirable if the ESD protection could be incorporated into the clamping circuit. The ability to rapidly drain or source current is important for both clamping and ESD protection. Older designs for clamping circuits that use current limiting resistors do not provide good ESD protection.
As metal oxide semiconductor technology has improved, MOS devices have been constructed with shorter gate lengths, thinner gate oxides and faster response times. As the gate oxide becomes thinner, the device must be powered with a lower voltage power supply to avoid breakdowns and leakage. Lower power supply voltages are also advantageous in reducing power consumption, decreasing heating, and increasing speed through smaller voltage swings.
Such lower voltage designs, however, need even more careful control over the input signal to prevent erratic operation due to ringing or other noise at the input. Good ESD protection for such designs is also critical.
In the following discussion, the positive terminal of the power supply will be referred to as Vdd. In older designs, this voltage is typically +5 volts, however, in newer designs, it may be 3.3, 2.5 or 1.8 volts. The lower voltage terminal of the power supply is referred to as Vss, and this voltage is usually at ground potential (zero volts).
A typical prior art five volt system has used a passive clamping circuit in which one diode is placed between the input terminal and Vss and one is placed between the input and Vdd. The diode between the input terminal and Vdd will conduct when the voltage at the input terminal rises sufficiently above the upper digital voltage to turn on the diode. Thus, this diode limits the input voltage to about 0.7 volts above the desired maximum input voltage, but permits 0.7 volt ringing around the upper digital voltage.
The second diode is positioned between the input terminal and Vss and conducts when the voltage at the input terminal falls one diode drop below the lower digital voltage (usually zero volts). This prevents ringing in excess of about 0.7 volts, but still permits ringing having a magnitude less than the value needed to turn on the passive diode clamp.
Passive clamp circuits of this type work in 5 volt systems because the amplitude of the ringing is relatively small compared to the difference between the upper and lower digital voltages. In lower voltage systems, such as a 3.3 volt system, this 0.7 volt ringing eats into the noise tolerance. In 2.5 and 1.8 volt systems, such ringing becomes an unacceptably large part of the signal swing, producing erratic operation in noisy environments.
During clamping by a passive diode clamp of this type, the excess signal voltage on the input is pulled towards (or clamped to) the positive Vdd supply voltage and the lower signal voltage state is pulled towards (or clamped to) the lower voltage supply (Vss or ground). In the active clamping circuit of the present invention, improved performance is achieved by activating the clamp as soon as or slightly before the input terminal voltage swings above or below the bounds set by the upper and lower digital voltages.
Performance is also improved by driving the input terminal voltage to the upper digital voltage via a connection to Vss when the input voltage is too high (above the upper voltage which is usually Vdd) and by driving the input terminal voltage to the lower digital voltage via a connection to Vdd when the input terminal voltage is too low (below the lower digital voltage which is usually Vss). This increases the speed at which the clamping circuit operates as compared to prior art designs which drive excessively low voltages through a connection to the low voltage supply (Vss) and excessively high voltages through a connection to the high voltage supply (Vdd).
To avoid some of the problems with older designs, source terminated drivers have been used in MOS circuits to lower the drive current of the driver into the net. Unfortunately, this increases delay and slows circuit response. Another problem with this solution is due to complex process tolerance requirements during construction of MOS devices. This results in poor control of the driver output impedance which also causes ringing.
For low voltage MOS designs, an active clamping circuit is needed, particularly in high performance low voltage designs where the clamp must hold the ringing to much less than the 0.7 volt limit of a passive diode clamp. Active clamp circuits employing transistors instead of diodes are known, but heretofore they have been bipolar in design, and thus are not suited for construction with the remainder of the MOS circuitry.
Another difficulty with prior art designs is that they have been similar to the passive diode clamp circuit described above. They have clamped the high logic signal to the higher Vdd power supply and the lower voltage logic signal to the lower voltage supply Vss. While this is functional, it cannot supply current as quickly to damp out ringing and noise as can a circuit designed according to the present invention. A further problem with prior art clamping circuit designs is the use of current limiting resistors which slow the clamping circuit response time and make them unsuitable for modern high speed MOS field effect transistor (MOSFET) circuits.
There is also a need for low power consumption designs for active clamping circuits and for circuits that may be turned off remotely, particularly during testing operations. These features are not available in prior art designs.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a clamping circuit specifically adapted for MOS circuits that turns on immediately at the desired clamping voltage, instead of at a diode voltage drop away from the desired voltage.
It is another object of the present invention to provide a clamping circuit that has high impedance during switching, for high switching speed, but low impedance when clamping (for rapid reduction of any ringing).
A further object of the invention is to provide a clamping circuit that may be switched on and off.
Still another object of the present invention is to provide a clamping circuit which has low power consumption.
It is yet another object of the present invention to provide a clamping circuit that provides ESD protection at the input of an attached circuit.
Still another object of the present invention is to provide a clamping circuit suitable for use with low voltage power supply systems, including 2.5 volt, 1.8 volt and lower voltage technologies.
A further object of the invention is to provide a clamping circuit that is compatible with and useful for silicon-on-insulator (SOI) and triple well technologies.
Another object of the present invention is to provide a an active clamping circuit which also operates when unpowered to provide ESD protection.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.